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Qualcomm and Google RISC it all for a shot at wearable redemption

Chip maker Qualcomm has ramped up its RISC-V efforts by agreeing with Google to co-develop processors for wearables running on the latter's Wear OS.

Nick Wood

October 18, 2023

3 Min Read
GooglexQualcomm

Chip maker Qualcomm has ramped up its RISC-V efforts by agreeing with Google to co-develop processors for wearables running on the latter’s Wear OS.

There’s nothing in the announcement about specific products or launch dates. Qualcomm instead has pitched it as an “expanded framework” that will help “pave the way for more products within the ecosystem to take advantage of custom CPUs that are low power and high performance.”

What makes this development significant though, is that it represents a shift by Qualcomm away from Arm’s proprietary RISC instruction set architecture (ISA) – available under licence for a fee – in favour of Google’s open source, RISC-V ISA, which is offered under a perpetual, royalty-free licence to anyone who fancies having a crack at building a processor.

By going open source, Google hopes to encourage the development of a wide variety of low-cost, power-efficient and customisable chipsets that lend themselves to a broad array of device types.

Qualcomm seems to be sold on the idea.

“We are excited to leverage RISC-V and expand our Snapdragon Wear platform as a leading silicon provider for Wear OS,” said Dino Bekis, vice president and general manager, wearables and mixed signal solutions, Qualcomm. “Our Snapdragon Wear platform innovations will help the Wear OS ecosystem rapidly evolve and streamline new device launches globally.”

As well as processors, Qualcomm and Google said they will also work together to foster the development of RISC-V compatible applications and software.

Indeed, in May, Qualcomm joined Google, Intel, Nvidia, MediaTek, Samsung and others to launch the RISC-V Software Ecosystem (RISE), a collaborative effort to accelerate the development of applications and software that run on RISC-V architecture.

In addition to chips and software, Qualcomm also recently got together with Bosch, Infineon, Nordic Semiconductor, and NXP to establish a new RISC-V focused hardware company. Based in Germany it will develop RISC-V based products that can be used as reference architecture. Its initial focus is on the automotive industry, but it also has eyes on mobile and IoT.

“We believe RISC-V’s open-source instruction set will increase innovation and has the potential to transform the industry,” Ziad Asghar, SVP of product management at Qualcomm, back in August.

For Qualcomm, the expanded framework with Google also represents a shot at redemption.

Qualcomm’s Snapdragon Wear chips have been powering Google smartwatches for years, but until recently they have been based on older processor production technology, making them less efficient and therefore competitive compared to wearable chips produced by the likes of Apple and Samsung.

A concerted effort to do better kicked off last summer, when Qualcomm announced the W5 and W5+ platform. These use a 4nm system-on-chip (SoC), a big improvement over its predecessor, which used a 12nm design. It brought Qualcomm more or less into line with Apple, which uses 7nm chips in its Apple Watch – although it is expected to introduce 3nm technology later this year – and Samsung’s Exynos chips, which use 5nm technology.

Adopting RISC-V takes Qualcomm’s commitment to improving its Wear OS offerings to the next level. It allows it to work more closely with Google to produce processors that are tailor made for Wear OS devices.

If all goes according to plan, it will no longer be a best-effort, one-size-fits-all platform, it will be the optimal platform for these devices.

 

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About the Author(s)

Nick Wood

Nick is a freelancer who has covered the global telecoms industry for more than 15 years. Areas of expertise include operator strategies; M&As; and emerging technologies, among others. As a freelancer, Nick has contributed news and features for many well-known industry publications. Before that, he wrote daily news and regular features as deputy editor of Total Telecom. He has a first-class honours degree in journalism from the University of Westminster.

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